Xilinx Zynq-7000 SoC ZC706 Evaluation Kit

Product Description

The Zynq®-7000 SoC ZC706 Evaluation Kit includes all the basic components of hardware, design tools, IP, and pre-verified reference designs including a targeted design, enabling a complete embedded processing platform and transceiver based designs including PCIe. The included pre-verified reference designs and industry-standard FPGA Mezzanine Connectors (FMC) allow scaling and customization with daughter cards. Please check the PetaLinux Software Development Kit page for information on the Xilinx processing systems.

Key Features & Benefits

• Optimized for quickly prototyping embedded applications using Zynq-7000 SoCs
• Hardware, design tools, IP, and pre-verified reference designs
• Demonstrates a embedded design, targeting video pipeline
• Advanced memory interface with
• 1GB DDR3 Component Memory
• 1GB DDR3 SODIM Memory

• Enabling serial connectivity with PCIe Gen2x4, SFP+ and SMA Pairs, USB OTG, UART, IIC
• Supports embedded processing with Dual ARM Cortex-A9 core processors
• Develop networking applications with 10-100-1000 Mbps Ethernet (RGMII​)
• Implement Video display applications with HDMI out
• Expand I/O with the FPGA Mezzanine Card (FMC) interface

Featured Xilinx Devices

Featuring the ROHS compliant ZC706 including the XC7Z045 FFG900 – 2 SoC

 

Board Features

Featuring the ZC706 Evaluation Board

Communication & Networking

• PCIe Gen2x4
• SFP+ and SMA Pairs
• GigE RGMII Ethernet (PS)
• USB OTG 1 (PS) - Host USB
• IIC Bus Headers/HUB (PS)
• 1 CAN with Wake on CAN (PS)
• USB UART (PS)

Expansion Connectors

• 1st FMC LPC expansion port (34 LVDS Pairs on LA Bus, 1 GT)
• 2nd FMC HPC expansion port (34 LVDS Pairs on LA Bus, 8 GT – No HA or HB bus)
• Dual Pmod (8 I/O Shared with LED’s)
• Single Pmod (4 I/O)
• IIC access to 8 I/O

Control & I/O

• 2 User Push Buttons/Dip Switch, 2 User LEDs
• IIC access to GPIO
• SDIO (SD Card slot)
• 3 User Push Buttons, 2 User Switches, 8 User LEDs
• IIC access to 8 I/O
• IIC access to a WTClock

Clocking

• 33MHz PS System Clock
• 200MHz PL Oscillator (Single-Ended Differential)
• SMA Connectors for external clock (Differential)
• GTX Reference Clock port with 2 SMA connectors
• OBSAI/CPRI – SFP+ Received clock
• EXT Config CLK

Configuration

• Onboard configuration circuitry
• 2X16MB Quad SPI Flash
• SDIO Card Interface (boot)
• PC4 and 20 pin JTAG ports

Memory

• DDR3 Component Memory 1GB (PS)
• DDR3 SODIM Memory 1GB (PL)
• 2X16MB Quad SPI Flash (config)
• IIC - 1 KB EEPROM

Analog

• AMS interface (Analog) System Monitor and also available for external sensor

Power

• 12 V wall adaptor
• Current measurement capability of supplies