Atum A5 Development Kit P0775

The Atum A5 Development Kit is Terasic’s first development kit in the Intel^® Agilex™ 5 FPGA portfolio. Powered by the largest Agilex^® 5 SoC FPGA with 656K LEs, the Atum A5 Development Kit is an out-of-the-box platform for advanced AI and vision application development.

With a rich set of interfaces ranging from 2.5G Ethernet, high-speed DDR4, QSFP+, PCIe Gen 3x4, FMC+ connectors, to MIPI connector and HDMI, the Atum A5 excels in a wide range of applications, including industrial networking, AI, embedded vision, medical and healthcare, video applications, and various other I/O expansion and high-speed applications!

Atum A5 Development Kit

Atum A5 System Side

• FPGA: A5ED065BB32AE4SR0 (656K LEs)
• Dimension: 155 mm x 160 mm
• Onboard USB-Blaster II
• Support ASx4 Configure Mode with 512Mbits QSPI Flash
• Active Heatsink
• Board Management System
• ◦ Power Monitor
• ◦ Temperature Monitor
• ◦ Auto Fan Control

FPGA Side

• HDMI Output Port (Support 1080P)
• DDR4-A: 4GB DDR4 with 32-bit data bus (no ECC). Shared with HPS
• DDR4-B: 4GB DDR4 with 32-bit data bus (no ECC)
• One FMC+ connector with 12 transceivers
• One 2.5G Ethernet PHY + RJ45
• One QSFP+ Port for 40 GbE network interface
• Two 2-lanes MIPI Connector for Camera/Display
• One PCIe Calbing Gen3 x4 Socket
• One 3.3V 2x20 DE-GPIO Header
• One 3.3V 2x6 TMD Header 
• User LED x4, Button x4, DIP Switch x4

HPS Side

• MicroSD Socket and 8GB eMMC
• DDR4-A: 4GB DDR4 with 32-bit data bus (no ECC). Shared with FPGA
• Gigabit Ethernet PHY + RJ45
• USB 3.1 Gen1 (5Gbps; use 1 transceiver) with USB Type-C connector
• UART to USB Port
• LED x1, Button x1, Cold Reset Button
• One 3.3V 2x6 GPIO Header. Including One I2C Bus

Software Support

• FPGA Example Code
• Linux BSP

Block Diagram

Connection to FMC Daughter Card

Connect to HDMI-FMC Daughter Card:

Connect to XTS-FMC Daughter Card:

Connect to 12G SDI-FMC Daughter Card:

Connection to MIPI Module

Connection to MIPI CSI-2 Camera Module: