DE25-STANDARD AGILEX 5 E SOC BRD

DE25-Standard Development and Education Kit

The new generation dev. kit for Altera  University Program! 

The DE25-Standard development kit is designed to meet the requirements of digital logic, embedded vision, AI and robotics applications. Powered by the Altera Agilex™ 5 SoC FPGA with 138K logic elements, the board delivers up to 2.5× performance improvement together with advanced features such as 1GB DDR4 memory with a 32-bit data bus, 64MB SDRAM, an 8-channel ADC header, GPIO expansion header, high-speed HSMC connector, and both black-and-white and color mini LCD modules. A comprehensive set of input and output interfaces, including switches, LEDs, and seven-segment displays, further extends its capability for experiments and project development.

In addition, the DE25-Standard integrates modern multimedia and vision interfaces, including an HDMI output port supporting 1080p, a two-lane MIPI CSI/DSI connector for camera and display, and a composite RCA jack for surveillance video. By leveraging these interfaces together with the AI Tensor Block built into the Agilex™ 5 FPGA, developers can build advanced AI-driven solutions in areas such as video processing, computer vision, and intelligent surveillance.

Included with DE25-Standard Development and Education Kit is a free license for Altera Quartus^® Pro Edition software — no additional license purchase is required. Developers can leverage full design and compilation capabilities of Quartus Pro without incurring licensing fees. Learn more about acquiring your free license.

DE25-Standard

• FPGA: A5ED013BB32AE4SR1
• Dimension: 166 mm x 130 mm
• Onboard USB-Blaster III
• Support ASx4 Configure Mode with 128Mbits QSPI Flash
• Optional Active Heatsink

FPGA side

• DDR4: 1GB DDR4 with 32-bit data bus (no ECC), shared with HPS.
• SDRAM: 64MB SDRAM with 32-bit data bus (no ECC).
• HDMI 1.4 Output Port (Support 1080P)
• One 2-lanes MIPI Connector for Camera/Display
• Composite video-In
• 24-bits audio codec: MIC-In, Line-In, and Line-Out
• 8-channel ADC with 2x5 header
• IR TX/RX
• One 3.3V 2x20 DE-GPIO Header
• One HSMC connector with 4 transceivers.
• User LED x10, Button x4, Slide Switch x10, 7-segment x6
• Temperature Sensor and Fan Controller

HPS side

• MicroSD Socket
• DDR4: 1GB DDR4 with 32-bit data bus (no ECC), shared with FPGA
• Gigabit Ethernet PHY + RJ45
• Two USB Host ports with USB Type-A connector
• UART to USB Port
• 128x64 LCD
• Accelerometer
• LED x1, Button x1, Cold Reset Button
• One 3.3V 1x6 GPIO Header

Software Support

• FPGA Example Code
• Linux BSP

Block Diagram

Connection to 2x20 GPIO Daugher Card

Connect LT24

Connect MTL2

Connect D8M

Connect SMK

Connect RFS2

Connection to HSMC Daugher Card

Connect HTG

Connect ADA

Connect DCC